Conventionally, an A/D converter for realizing a fast operation, a small area and small power consumption includes, as shown in FIG. 14, a preamp row 1003 composed of one or more preamps 1002 at a previous stage of a comparator row 1005 composed of one or more comparators 1004. In many cases, the comparator row 1005 performs comparison while interpolating the output voltage of the preamp row 1003. The effects attained by providing the preamp row 1003 at the previous stage of the comparator row 1005 and by performing the comparison while interpolating the output voltage of the preamp row 1003 are that the input capacity of the A/D converter can be reduced first, that the offset of each comparator can be reduced secondly and that the input dynamic range of each comparator 1004 can be set large thirdly (see, for example, Non-patent Document 1 and Non-patent Document 2 for these effects).
Non-patent Document 1: Koji Sushihara and four others, “A 6b 800M Sample/s CMOS A/D Converter”, 2000 Feb. 7-9, ISSCC2000/SESSION 26/ANALOG TECHNIQUES/PAPER WP 26.2
Non-patent Document 2: Koji Sushihara, Akira Matsuzawa, “A 7b 450M Sample/s 50 mW CMOS ADC in 0.3 mm^2”, 2002 Feb. 3-7, ISSCC2002/SESSION 10/HIGH-SPEED ADCs/10.3